The present invention relates generally to fuses and more specifically to vertical fuses.
Integrated circuit designers are always attempting to reduce the amount of chip area needed for specific devices. In memory arrays, efforts to reduce the size have included using vertical fuses instead of horizontal fuses. To further increase the density, an oxide forms the vertical fusible link separating a top contact from a diode or bipolar transistor in the substrate. A typical example are U.S. Pat. Nos. 3,576,549 to Hess et al.; 3,668,655 to Allen and 3,781,977 to Hulmes.
The use of epitaxial or polycrystalline layers as fuse elements over the emitter of an emitter follower array is shown in U.S. Pat. No. 4,312,046 to Taylor. These vertical fuses are programmed by electromigration of the aluminum top contact through the fuse layer. In an effort to protect the emitter follower transistor from the avalanche induced migration of Taylor, a barrier layer may be provided between the fusible element and the emitter. This is specifically shown in U.S. Pat. No. 4,424,578 to Miyamoto.
Although these patents show vertical fuses which have increased the packing density on the surface of a die, they generally include multiple masking steps to form the emitter opening to produce the emitter as well as separate and distinct steps to form the vertical fuse element.
Thus, it is a primary object of the present invention to provide a process for fabricating an improved vertical fuse having minimal processing steps.
Another object of the present invention is to provide a process for fabricating vertical fuses with a minimal number of steps with alignment of the vertical fuse to the emitter.
Still another object of the present invention is to provide a method of fabricating a vertical fuse with a minimum number of masking steps which is also compatible with a combined insulated gate field effect transistor and bipolar memory circuit.
These and other objects of the invention are attained by forming a mask on a first insulative layer on a substrate having an opening corresponding to the to be formed emitter region, introducing impurities into the opening followed by forming an emitter aperture in the first insulative layer using the mask layer. The mask layer is removed and the substrate is oxidized to form a thin oxide fuse region in the emitter aperture. A top electrode is formed on the thin oxide region. Thus, a single mask is used for the formation of the emitter regions, the emitter aperture, and the subsequently formed thin oxide fuse region. Preferably, the emitter is formed by ion implanting the impurities using the mask layer.
As an alternative, the mask layer would be used only to form an emitter aperture in the first layer followed by oxidizing to form the thin oxide fuse and providing a doped polycrystalline material as the top gate. After rupture of the thin oxide fuse, the dopant of the polycrystalline top gate will diffuse impurities into the substrate to form the emitter region. The doped polycrystalline top electrode may also be the gate of an insulated gate field effect transistor formed simultaneously with the bipolar transistor and vertical fuse.
As another alternative, the top electrode may be of a metal and the substrate having an appropriate impurity concentration such that upon rupture of the thin fuse region, the top metal contact comes into contact with the surface of the substrate and forms a metal to substrate rectifying junction as the emitter base junction. In all embodiments, the first insulative layer is thicker than the thin oxide layer and thinner than the field oxide. When formed in conjunction with insulated gate field effect transistors, the gate oxide layer step may form all or a portion of the first insulative layer in which the vertical oxide fuse is formed.
As a further alternative, the mask layer is used to form an emitter aperture in the first layer. The mask is removed and impurities are introduced from a gaseous atmosphere. After washing the aperture, the thin oxide fuse is formed in the aperture by oxidation. The thin oxide fuse and the source of impurities can be formed simultaneously from a common gaseous environment. The impurities are diffused by subsequent heating steps.
An integrated circuit of the present invention would generally include a substrate, a field oxide on the substrate having a first thickness, at least one bipolar transistor, a first insulative layer having a second thickness less than the first thickness over the bipolar transistor, a second insulative layer having a third thickness less than the second thickness over the formed or to be formed emitter region and having a substantially equal area to the lateral area of a formed or to be formed emitter region. A top electrode on the second insulative layer produces a vertical fuse between the top electrode and the bipolar transistor.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.